Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 59bad947180ddc22665e8b2b5f8f9ef65e8aab7f / drivers / gpu / drm / i915 / intel_pm.c
  1. 59bad94 drm/i915: Rename the forcewake get/put functions by Mika Kuoppala · 10 years ago
  2. 6e3c971 drm/i915: Make intel_crtc->config a pointer by Ander Conselvan de Oliveira · 10 years ago
  3. 2d112de drm/i915: Embedded struct drm_crtc_state in intel_crtc_state by Ander Conselvan de Oliveira · 10 years ago
  4. 5cec258 drm/i915: Rename struct intel_crtc_config to intel_crtc_state by Ander Conselvan de Oliveira · 10 years ago
  5. af5a75a Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv"" by Ville Syrjälä · 10 years ago
  6. 3cbdb48 drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV by Ville Syrjälä · 10 years ago
  7. cad725f drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimal by Ville Syrjälä · 10 years ago
  8. 160614a drm/i915: Disable RC6 before configuring in on VLV/CHV by Ville Syrjälä · 10 years ago
  9. 095acd5 drm/i915: New offset for reading frequencies on CHV. by Deepak S · 10 years ago
  10. d3e7a0d Merge tag 'drm-intel-next-2015-01-17' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  11. 281d1bb Merge remote-tracking branch 'origin/master' into drm-next by Dave Airlie · 10 years ago
  12. e85a5c7 Revert "drm/i915/chv: Use timeout mode for RC6 on chv" by Rodrigo Vivi · 10 years ago
  13. 0a87a2d Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  14. f24eeb1 drm/i915: vlv: sanitize RPS interrupt mask during GPU idling by Imre Deak · 10 years ago
  15. 59d02a1 drm/i915: fix HW lockup due to missing RPS IRQ workaround on GEN6 by Imre Deak · 10 years ago
  16. 63a3451 drm/i915: gen9: fix RPS interrupt routing to CPU vs. GT by Imre Deak · 10 years ago
  17. adc3184 Merge tag 'drm-intel-next-2014-12-19' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
  18. 9441159 drm/i915: Make sample_c messages go faster on Haswell. by Kenneth Graunke · 10 years ago
  19. 5a0afd4 drm/i915/chv: Use timeout mode for RC6 on chv by Deepak S · 10 years ago
  20. dbea3ce drm/i915: sanitize RPS resetting during GPU reset by Imre Deak · 10 years ago
  21. d9d8e6b drm/i915/skl: Correcting the flushing of pipe by Sonika Jindal · 10 years ago
  22. a712f8e drm/i915/skl: Correctly updating sprite wm parameter by Sonika Jindal · 10 years ago
  23. 7ff0ebc drm/i915: Move FBC stuff to intel_fbc.c by Rodrigo Vivi · 10 years ago
  24. 9853325 drm/i915/bdw: Fix the write setting up the WIZ hashing mode by Damien Lespiau · 10 years ago
  25. d972d6e drm/i915: Convert pxvid to extvid lookup table to a function by Mika Kuoppala · 10 years ago
  26. 99990f1 drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave by Imre Deak · 10 years ago
  27. 2837ac4 drm/i915: vlv: increase timeout when setting idle GPU freq by Imre Deak · 10 years ago
  28. 6985b35 drm/i915: Update ring freq for full gpu freq range by Tom O'Rourke · 10 years ago
  29. c7f3153 drm/i915: change initial rps frequency for gen8 by Tom O'Rourke · 10 years ago
  30. f4ab408 drm/i915: Keep min freq above floor on HSW/BDW by Tom O'Rourke · 10 years ago
  31. 93ee292 drm/i915: Use efficient frequency for HSW/BDW by Tom O'Rourke · 10 years ago
  32. 54499b2 Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  33. 2eb5252 drm/i915: disable rps irqs earlier during suspend/unload by Imre Deak · 10 years ago
  34. d4d70aa drm/i915: sanitize rps irq disabling by Imre Deak · 10 years ago
  35. 3cc134e drm/i915: sanitize rps irq enabling by Imre Deak · 10 years ago
  36. e534770 drm/i915: move rps irq disable one level up by Imre Deak · 10 years ago
  37. 151a49d drm/i915: Extend pcode mailbox interface by Tom O'Rourke · 10 years ago
  38. ab3fb15 drm/i915: Change CHV SKU400 GPU freq divider to 10 by Ville Syrjälä · 10 years ago
  39. 80b83b6 drm/i915: Add missing newline to 'DDR speed' debug messages by Ville Syrjälä · 10 years ago
  40. dd06f88 drm/i915: Refactor vlv/chv GPU frequency divider setup by Ville Syrjälä · 10 years ago
  41. ce611ef drm/i915: Improve PCBR debug information by Ville Syrjälä · 10 years ago
  42. 8d40c3a drm/i915: Warn if GPLL isn't used on vlv/chv by Ville Syrjälä · 10 years ago
  43. c8e9627 drm/i915: Add a name for the Punit GPLLENABLE bit by Ville Syrjälä · 10 years ago
  44. 9a3b9c7 drm/i915: Silence valleyview_set_rps() by Ville Syrjälä · 10 years ago
  45. 2208d65 drm/i915: drop WaSetupGtModeTdRowDispatch:snb by Daniel Vetter · 10 years ago
  46. f5ed50c drm/i915: Let's hope future platforms will use the same WM code as SKL by Damien Lespiau · 10 years ago
  47. dddab34 drm/i915: Clear PCODE_DATA1 on SNB+ by Damien Lespiau · 10 years ago
  48. c6e8f39 drm/i915: Read the CCK fuse register from CCK by Ville Syrjälä · 10 years ago
  49. b900b94 drm/i915: move rps irq enable/disable to i915_irq.c by Imre Deak · 10 years ago
  50. 20415c5 drm/i915: unify gen6/gen8 rps irq enable/disable by Imre Deak · 10 years ago
  51. a72fbc3 drm/i915: unify gen6/gen8 pm irq helpers by Imre Deak · 10 years ago
  52. 3e470ea drm/i915/chv: Remove pre-production workarounds by Arun Siluvery · 10 years ago
  53. 20e4936 drm/i915/skl: Enable Gen9 RC6 by Zhe Wang · 10 years ago
  54. d21b795 drm/i915/skl: Log the order in which we flush the pipes in the WM code by Damien Lespiau · 10 years ago
  55. 0e8fb7b drm/i915/skl: Flush the WM configuration by Damien Lespiau · 10 years ago
  56. 34bb56a drm/i915/skl: Stage the pipe DDB allocation by Damien Lespiau · 10 years ago
  57. 5d374d9 drm/i915/skl: Reduce the indentation level in skl_write_wm_values() by Damien Lespiau · 10 years ago
  58. afb024a drm/i915/skl: Correctly align skl_compute_plane_wm() arguments by Damien Lespiau · 10 years ago
  59. 9414f56 drm/i915/skl: Rework when the transition WMs are computed by Damien Lespiau · 10 years ago
  60. 407b50f drm/i915/skl: Move all the WM compute functions in one place by Damien Lespiau · 10 years ago
  61. e6d6617 drm/i915/skl: Make res_blocks/lines intermediate values 32 bits by Damien Lespiau · 10 years ago
  62. 21fca25 drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm() by Damien Lespiau · 10 years ago
  63. 16160e3 drm/i915/skl: Make 'end' of the DDB allocation entry exclusive by Damien Lespiau · 10 years ago
  64. 08db665 drm/i915/skl: Check the DDB state at modeset by Damien Lespiau · 10 years ago
  65. a269c58 drm/i915/skl: Read back the DDB allocation hw state by Damien Lespiau · 10 years ago
  66. 53b0deb drm/i915/skl: Store the new WM state at the very end of the update by Damien Lespiau · 10 years ago
  67. 4f94738 drm/i915/gen9: Disable WM if corresponding latency is 0 by Vandana Kannan · 10 years ago
  68. 367294b drm/i915/gen9: Add 2us read latency to WM level by Vandana Kannan · 10 years ago
  69. 3078999 drm/i915/skl: Read the pipe WM HW state by Pradeep Bhat · 10 years ago
  70. 8211bd5 drm/i915/skl: Program the DDB allocation by Damien Lespiau · 10 years ago
  71. b9cec07 drm/i915/skl: Allocate DDB portions for display planes by Damien Lespiau · 10 years ago
  72. 2d41c0b drm/i915/skl: SKL Watermark Computation by Pradeep Bhat · 10 years ago
  73. 2ac96d2 drm/i915/skl: Definition of SKL WM param structs for pipe/plane by Pradeep Bhat · 10 years ago
  74. 2af30a5 drm/i915/skl: Read the Memory Latency Values for WM computation by Pradeep Bhat · 10 years ago
  75. 5e56ba4 drm/i915/chv: Use 16 and 32 for low and high drain latency precision. by Rodrigo Vivi · 10 years ago
  76. 101b376 drm/i915/bdw: Remove BDW preproduction W/As until C stepping. by Rodrigo Vivi · 10 years ago
  77. 58abf1d drm/i915: Do not export RC6p and RC6pp if they don't exist by Rodrigo Vivi · 10 years ago
  78. a8cbd45 Merge branch 'drm-intel-next-fixes' into drm-intel-next by Daniel Vetter · 10 years ago
  79. 2aeb7d3 drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/ by Daniel Vetter · 10 years ago
  80. 9c065a7 drm/i915: Extract intel_runtime_pm.c by Daniel Vetter · 10 years ago
  81. 955e36d Merge branch 'topic/skl-stage1' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  82. 6795686 drm/i915: Don't spam dmesg with rps messages on vlv/chv by Ville Syrjälä · 10 years ago
  83. 7526ed7 Revert "drm/i915/bdw: BDW Software Turbo" by Daniel Vetter · 10 years ago
  84. 1d73c2a drm/i915: Minimize the huge amount of unecessary fbc sw cache clean. by Rodrigo Vivi · 10 years ago
  85. c83155a drm/i915/skl: Move gen9 pm initialization into its own branch by Damien Lespiau · 11 years ago
  86. 3ca5da4 drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl by Damien Lespiau · 11 years ago
  87. 91e41d1 drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl by Damien Lespiau · 11 years ago
  88. acd5c34 drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl by Damien Lespiau · 11 years ago
  89. 08524a9f drm/i915/skl: Restore pipe B/C interrupts by Satheeshakrishna M · 11 years ago
  90. da2078c drm/i915/skl: Provide a placeholder for init_clock_gating() by Damien Lespiau · 12 years ago
  91. 9adccc6 drm/i915: add SW tracking to FBC enabling by Paulo Zanoni · 10 years ago
  92. d2dee86 drm/i915: extract intel_init_fbc() by Paulo Zanoni · 10 years ago
  93. 342e36c drm/i915: Avoid reading fbc registers in vain when fbc was never enabled. by Rodrigo Vivi · 10 years ago
  94. 01d06e9 drm/i915: Only flush fbc on sw when fbc is enabled. by Rodrigo Vivi · 10 years ago
  95. d6feb19 drm/i915: Limit the watermark to at least 8 entries on gen2/3 by Ville Syrjälä · 10 years ago
  96. 773538e8 drm/i915: Reset power sequencer pipe tracking when disp2d is off by Ville Syrjälä · 10 years ago
  97. 5aef600 drm/i915: Rename global latency_ns variable by Chris Wilson · 10 years ago
  98. 1038392 drm/i915: Disable trickle feed for gen2/3 by Ville Syrjälä · 10 years ago
  99. 9d53910 drm/i915: Fix gen2 planes B and C max watermark value by Ville Syrjälä · 10 years ago
  100. 00e1e62 drm/i915: Init some CHV workarounds via LRIs in ring->init_context() by Ville Syrjälä · 10 years ago