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gerrit-public.fairphone.software / kernel / msm-4.9 / 72b54df9a5eff47c4d58828cb48aa10586ce5480 / drivers / clk / sunxi-ng / ccu-sun6i-a31.c
  1. 2c304e4 clk: sunxi: A31: Fix wrong AHB gate number by Andre Przywara · 6 years ago
  2. bdbd915 clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops by Chen-Yu Tsai · 7 years ago
  3. 5859027 clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision by Chen-Yu Tsai · 7 years ago
  4. 7084a27 clk: sunxi-ng: A31: Fix spdif clock register by Marcus Cooper · 8 years ago
  5. 0e051f1 clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset by Chen-Yu Tsai · 7 years ago
  6. 867f780 clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock by Chen-Yu Tsai · 8 years ago
  7. 95881a5 clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it by Chen-Yu Tsai · 8 years ago
  8. a17b9e4 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent by Chen-Yu Tsai · 8 years ago
  9. 5254223 clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk by Chen-Yu Tsai · 8 years ago
  10. d613782 clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs by Chen-Yu Tsai · 8 years ago
  11. d832fdd clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks by Chen-Yu Tsai · 8 years ago
  12. c6e6c96 clk: sunxi-ng: Add A31/A31s clocks by Chen-Yu Tsai · 8 years ago