Log - 8610d09a40c10dea55dada151cf85cce253f511c - kernel/msm-4.9

9535c47 drm/i915: cope with large i2c transfers by Dmitry Torokhov · 10 years ago
6c826f3 drm/i915: Add fault address to error state for gen8 and gen9 by Mika Kuoppala · 10 years ago
6f4b12f8 drm/i915: Use down ei for manual Baytrail RPS calculations by Chris Wilson · 10 years ago
43cf3bf drm/i915: Improved w/a for rps on Baytrail by Chris Wilson · 10 years ago
de43ae9 drm/i915/skl: Added new macros by Akash Goel · 10 years ago
f499896 drm/i915: Use FW_WM() macro for older gmch platforms too by Ville Syrjälä · 10 years ago
1566597 drm/i915: Add polish to VLV WM shift+mask operations by Ville Syrjälä · 10 years ago
fc1ac8d drm/i915: Disable DDR DVFS on CHV by Ville Syrjälä · 10 years ago
cfb4141 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV by Ville Syrjälä · 10 years ago
1e69cd7 drm/i915: Program PFI credits for VLV by Vidya Srinivas · 10 years ago
ae80152 drm/i915: Rewrite VLV/CHV watermark code by Ville Syrjälä · 10 years ago
9cbe40c drm/i915: Update prop, int co-eff and gain threshold for CHV by Vijay Purushothaman · 10 years ago
de3a0fd drm/i915: Initialize CHV digital lock detect threshold by Vijay Purushothaman · 10 years ago
a945ce7e drm/i915: Disable M2 frac division for integer case by Vijay Purushothaman · 10 years ago
5575f03 drm/i915/chv: Add CHV HW status to SSEU status by Jeff McGee · 10 years ago
c93043a drm/i915/chv: Determine CHV slice/subslice/EU info by Jeff McGee · 10 years ago
c6beb13 drm/i915: Make sure PND deadline mode is enabled on VLV/CHV by Ville Syrjälä · 10 years ago
b500472 drm/i915: Read out display FIFO size on VLV/CHV by Ville Syrjälä · 10 years ago
341c526 drm/i915: Hide VLV DDL precision handling by Ville Syrjälä · 10 years ago
1203051 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines by Ville Syrjälä · 10 years ago
edf6056 drm/i915: Reduce CHV DDL multiplier to 16/8 by Ville Syrjälä · 10 years ago
fd0753c drm/i915: Fix trivial typos in comments and warning message by Yannick Guerrini · 10 years ago
6fa7aec drm/i915: Support for RR switching on VLV by Vandana Kannan · 10 years ago
b766879 drm/i915/skl: Tune IZ hashing when subslices are unbalanced by Damien Lespiau · 10 years ago
0cea650 drm/i915: Request full SSEU enablement on Gen9 by Jeff McGee · 10 years ago
7f992ab drm/i915/skl: Add SKL HW status to SSEU status by Jeff McGee · 10 years ago
3873218 drm/i915/skl: Determine SKL slice/subslice/EU info by Jeff McGee · 10 years ago
d0bbbc4 drm/i915/skl: Implement WaDisablePowerCompilerClockGating by Damien Lespiau · 10 years ago
d3eee4b drm/i915: Add new PHY reg definitions for lock threshold by Vijay Purushothaman · 10 years ago
77719d2 drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement by Damien Lespiau · 10 years ago
183c6da drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken by Damien Lespiau · 10 years ago
65ca751 drm/i915/skl: Implement WaBarrierPerformanceFixDisable by Damien Lespiau · 10 years ago
e2db707 drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl by Damien Lespiau · 10 years ago
2caa3b2 drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS by Damien Lespiau · 10 years ago
81e231a drm/i915/skl: Implement WaDisableHDCInvalidation by Damien Lespiau · 10 years ago
8bc0ccf drm/i915/skl: Implement WaDisableLSQCROPERFforOCL by Damien Lespiau · 10 years ago
9370cd9 drm/i915/skl: Implement WaDisablePartialResolveInVc by Damien Lespiau · 10 years ago
9253c2e drm/i915/skl: Implement WaSetGAPSunitClckGateDisable by Damien Lespiau · 10 years ago
2db59d5 drm/i915: Detect eDRAM with the enabled bit only by Damien Lespiau · 10 years ago
35cb6f3 drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent by Damien Lespiau · 10 years ago
cac23df drm/i915/gen9: Implement WaEnableYV12BugFixInHalfSliceChicken7 by Nick Hoath · 10 years ago
8424171 drm/i915/gen9: h/w w/a: syncing dependencies between camera and graphics by Nick Hoath · 10 years ago
94dd513 drm/i915/skl: Implementation of SKL display power well support by Satheeshakrishna M · 10 years ago
e3d9984 drm/i915/skl: Enabling PSR on Skylake by Sonika Jindal · 10 years ago
38c2352 drm/i915/skl: Gen9 coarse power gating by Zhe Wang · 10 years ago
095acd5 drm/i915: New offset for reading frequencies on CHV. by Deepak S · 10 years ago
693d11c drm/i915/chv: Populate total EU count on Cherryview by Deepak S · 10 years ago
d60de81 drm/i915: Improve HiZ throughput on Cherryview. by Kenneth Graunke · 10 years ago
0a87a2d Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued by Daniel Vetter · 10 years ago
9441159 drm/i915: Make sample_c messages go faster on Haswell. by Kenneth Graunke · 10 years ago
2c55018 drm/i915: Disable PSMI sleep messages on all rings around context switches by Chris Wilson · 10 years ago
148b83d drm/i915: Invalidate media caches on gen7 by Chris Wilson · 10 years ago
c61200c drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist by Jordan Justen · 10 years ago
9f49c37 drm/i915: save/restore GMBUS freq across suspend/resume on gen4 by Jesse Barnes · 10 years ago
eb73667 drm/i915: Engage the DP scramble reset for pipe C on CHV by Ville Syrjälä · 10 years ago
86ef630 drm/i915: Add MI_SET_APPID cmd to cmd parser tables by Michael H. Nguyen · 10 years ago
9853325 drm/i915/bdw: Fix the write setting up the WIZ hashing mode by Damien Lespiau · 10 years ago
a9da9bc drm/i915: Pixel Clock changes for DSI dual link by Gaurav K Singh · 10 years ago
369602d drm/i915: Add support for port enable/disable for dual link configuration by Gaurav K Singh · 10 years ago
8edfbb8 drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/ by Ville Syrjälä · 10 years ago
e7d7cad drm/i915/dsi: clean up MIPI DSI pipe vs. port usage by Jani Nikula · 10 years ago
c8f7df5 drm/i915: Add PSR registers for PSR VLV/CHV. by Rodrigo Vivi · 10 years ago
59ea905 drm/i915: Implement GPU reset for 915/945 by Ville Syrjälä · 10 years ago
73bbf6b drm/i915: Fix gen4 GPU reset by Ville Syrjälä · 10 years ago
656bfa3 drm/i915: Pin tiled objects for L-shaped configs by Daniel Vetter · 10 years ago
93ee292 drm/i915: Use efficient frequency for HSW/BDW by Tom O'Rourke · 10 years ago
eb88bd1 drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0() by Ville Syrjälä · 10 years ago
c8e9627 drm/i915: Add a name for the Punit GPLLENABLE bit by Ville Syrjälä · 10 years ago
dddab34 drm/i915: Clear PCODE_DATA1 on SNB+ by Damien Lespiau · 10 years ago
88e0470 drm/i915/skl: AUX irqs have moved by Jesse Barnes · 10 years ago
bd2e244 drm/i915/skl: fetch, enable/disable pfit as needed v2 by Jesse Barnes · 10 years ago
830c81d drm/i915/skl: Implement queue_flip by Damien Lespiau · 10 years ago
540e732 drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock by Satheeshakrishna M · 10 years ago
326ac39 drm/i915/skl: Register definitions for SKL Clocks by Satheeshakrishna M · 10 years ago
f1f55cc drm/i915: Add the predicate source registers to the register whitelist by Neil Roberts · 10 years ago
95289009 drm/i915/chv: Add new workarounds for chv by Arun Siluvery · 10 years ago
eb84f97 Merge remote-tracking branch 'airlied/drm-next' into HEAD by Daniel Vetter · 10 years ago
82910ac drm/i915: make pipe/port based audio valid accessors easier to use by Jani Nikula · 10 years ago
38cff0b drm/i915/skl: Gen9 Forcewake by Zhe Wang · 10 years ago
8211bd5 drm/i915/skl: Program the DDB allocation by Damien Lespiau · 10 years ago
fae1267 drm/i915/skl: Register definitions and macros for SKL Watermark regs by Pradeep Bhat · 10 years ago
2af30a5 drm/i915/skl: Read the Memory Latency Values for WM computation by Pradeep Bhat · 10 years ago
c46f111 drm/i915: clean up and clarify audio related register defines by Jani Nikula · 10 years ago
1f9e14b Merge tag 'topic/core-stuff-2014-11-05' of git://anongit.freedesktop.org/drm-intel into drm-next by Dave Airlie · 10 years ago
6ca2aeb drm/i915: Add support for CHV pipe B sprite CSC by Ville Syrjälä · 10 years ago
c14b048 drm/i915: Initialize new chv primary plane and pipe blender registers by Ville Syrjälä · 10 years ago
4398ad4 drm/i915: Add rotation support for cursor plane (v5) by Ville Syrjälä · 10 years ago
5e56ba4 drm/i915/chv: Use 16 and 32 for low and high drain latency precision. by Rodrigo Vivi · 10 years ago
142d2ec drm/i915: Fix chv PCS DW11 register defines by Ville Syrjälä · 10 years ago
1447dde drm/i915/skl: Add 180 degree HW rotation support by Sonika Jindal · 10 years ago
a8cbd45 Merge branch 'drm-intel-next-fixes' into drm-intel-next by Daniel Vetter · 10 years ago
32197aa gpu:drm: Fix typo in Documentation/DocBook/drm.xml by Masanari Iida · 10 years ago
570e2a7 drm/i915: Clear TX FIFO reset master override bits on chv by Ville Syrjälä · 10 years ago
a02ef3c drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv by Ville Syrjälä · 10 years ago
5ca476f drm/i915: De-magic the PSR AUX message by Ville Syrjälä · 10 years ago
ebb69c9 drm/i915: Enable pixel replicated modes on BDW and HSW. by Clint Taylor · 10 years ago
955e36d Merge branch 'topic/skl-stage1' into drm-intel-next-queued by Daniel Vetter · 10 years ago
da09654 drm/i915/bdw: WaDisableFenceDestinationToSLM by Rodrigo Vivi · 10 years ago
7526ed7 Revert "drm/i915/bdw: BDW Software Turbo" by Daniel Vetter · 10 years ago
dc2a41b drm/i915/skl: Implement drm_plane vfuncs by Damien Lespiau · 11 years ago