1. d4f513f Clk: SPEAr1340: Update sys clock parent array by Vipul Kumar Samar · 12 years ago
  2. d9ba8db clk: SPEAr1340: Fix clk enable register for uart1 and i2c1. by Vipul Kumar Samar · 12 years ago
  3. a8f4bf0 Clk:spear6xx:Fix: Rename clk ids within predefined limit by Vipul Kumar Samar · 12 years ago
  4. 5cfc545 Clk:spear3xx:Fix: Rename clk ids within predefined limit by Vipul Kumar Samar · 12 years ago
  5. e28f1aa clk:spear1310:Fix: Rename clk ids within predefined limit by Vipul Kumar Samar · 12 years ago
  6. 5cb6a9b clk:spear1340:Fix: Rename clk ids within predefined limit by Vipul Kumar Samar · 12 years ago
  7. 3a35fc3 clk: SPEAr600: Fix ethernet clock name for DT based probing by Stefan Roese · 12 years ago
  8. 10d8935 Viresh has moved by Viresh Kumar · 12 years ago
  9. 0b928af SPEAr13xx: Add common clock framework support by Viresh Kumar · 12 years ago
  10. 5df33a6 SPEAr: Switch to common clock framework by Viresh Kumar · 13 years ago
  11. a45896b SPEAr: clk: Add General Purpose Timer Synthesizer clock by Viresh Kumar · 13 years ago
  12. 270b9f4 SPEAr: clk: Add Fractional Synthesizer clock by Viresh Kumar · 13 years ago
  13. 5335a63 SPEAr: clk: Add Auxiliary Synthesizer clock by Viresh Kumar · 13 years ago
  14. 55b8fd4 SPEAr: clk: Add VCO-PLL Synthesizer clock by Viresh Kumar · 13 years ago