1. 9de44aa Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-next by Russell King · 9 years ago
  2. b2c3e38 ARM: redo TTBR setup code for LPAE by Russell King · 9 years ago
  3. e748994 ARM: 8353/1: mm: Fix Cortex-A8 erratum 430973 segfaults for bootloaders and multiarch by Tony Lindgren · 9 years ago
  4. a6d74678 ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUs by Russell King · 9 years ago
  5. 6ebbf2c ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ by Russell King · 10 years ago
  6. b6ccb98 ARM: 7954/1: mm: remove remaining domain support from ARMv6 by Will Deacon · 11 years ago
  7. bf3f0f3 ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2 by Will Deacon · 11 years ago
  8. 8bd26e3 arm: delete __cpuinit/__CPUINIT usage from all ARM users by Paul Gortmaker · 11 years ago
  9. ae8a8b9 ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead by Will Deacon · 11 years ago
  10. 251019f ARM: 7650/1: mm: replace direct access to mm->context.id with new macro by Ben Dooks · 12 years ago
  11. 26ffd0d ARM: mm: introduce present, faulting entries for PAGE_NONE by Will Deacon · 12 years ago
  12. dbf62d5 ARM: mm: introduce L_PTE_VALID for page table entries by Will Deacon · 12 years ago
  13. 0cbbbad ARM: mm: don't use the access flag permissions mechanism for classic MMU by Will Deacon · 12 years ago
  14. 575320d ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process by Will Deacon · 12 years ago
  15. 7fec1b5 ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs by Catalin Marinas · 13 years ago
  16. 3c5f7e7 ARM: Use TTBR1 instead of reserved context ID by Will Deacon · 13 years ago
  17. 8d2cd3a ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S by Catalin Marinas · 13 years ago