1. e9e24fa MIPS: pm-cps: Drop manual cache-line alignment of ready_count by Paul Burton · 7 years ago
  2. ba75050 MIPS: pm-cps: Generate idle state entry code when CPUs are onlined by Paul Burton · 8 years ago
  3. 7745199 MIPS: pm-cps: Support CM3 changes to Coherence Enable Register by Matt Redfearn · 8 years ago
  4. 929d4f5 MIPS: pm-cps: Add MIPSr6 CPU support by Matt Redfearn · 8 years ago
  5. 15ea26c MIPS: pm-cps: Remove selection of sync types by Matt Redfearn · 8 years ago
  6. 90b084b MIPS: pm-cps: Use MIPS standard completion barrier by Matt Redfearn · 8 years ago
  7. 85e540b MIPS: pm-cps: Use MIPS standard lightweight ordering barrier by Matt Redfearn · 8 years ago
  8. f6b43d9354 MIPS: pm-cps: Update comments on barrier instructions by Matt Redfearn · 8 years ago
  9. b97d0b9 MIPS: pm-cps: Change FSB workaround to CPU blacklist by Matt Redfearn · 8 years ago
  10. 97f2645 tree-wide: replace config_enabled() with IS_ENABLED() by Masahiro Yamada · 8 years ago
  11. 0f2a148 MIPS: pm-cps: Avoid offset overflow on MIPSr6 by Markos Chandras · 8 years ago
  12. 92a76f6 MIPS: Fix misspellings in comments. by Adam Buchbinder · 8 years ago
  13. 4e88a86 MIPS: Add cases for CPU_I6400 by Markos Chandras · 9 years ago
  14. c90e49f MIPS: {pm,smp}-cps: use cpu_vpe_id macro by Paul Burton · 10 years ago
  15. 064231e MIPS: pm-cps: Prevent use of mips_cps_* without CPS SMP by Paul Burton · 10 years ago
  16. 7c5491b MIPS: pm-cps: convert smp_mb__*() by Paul Burton · 10 years ago
  17. 3179d37 MIPS: pm-cps: add PM state entry code for CPS systems by Paul Burton · 10 years ago