drm: rcar-du: Refactor DEFR8 feature
Rename the feature from RCAR_DU_FEATURE_DEFR8 to
RCAR_DU_FEATURE_EXT_CTRL_REGS to cover all extended control registers in
addition to the DEFR8 register.
Usage of the feature is refactored to optimize runtime operation and
prepare for external clock support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 4e7614b..7b64282 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -48,9 +48,6 @@
{
u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
- if (!rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_DEFR8))
- return;
-
/* The DEFR8 register for the first group also controls RGB output
* routing to DPAD0
*/
@@ -69,7 +66,8 @@
rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
- rcar_du_group_setup_defr8(rgrp);
+ if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS))
+ rcar_du_group_setup_defr8(rgrp);
/* Use DS1PR and DS2PR to configure planes priorities and connects the
* superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
@@ -149,6 +147,9 @@
{
int ret;
+ if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
+ return 0;
+
/* RGB output routing to DPAD0 is configured in the DEFR8 register of
* the first group. As this function can be called with the DU0 and DU1
* CRTCs disabled, we need to enable the first group clock before