tree 89295d33fcb50b73dba25302a9979fb013cf9cd0
parent 648e3a5bdddf8e7ad9c27450ac368b8bccd807a5
author Jayachandran B <jayachandran.b@intel.com> 1450431723 +0530
committer Mark Brown <broonie@kernel.org> 1452428341 +0000

ASoC: Intel: Skylake: fix reset controller sequencing

MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>