| commit | 0f82cb9211f800f77636af11f0670e5fc6de6256 | [log] [tgz] |
|---|---|---|
| author | James Bottomley <James.Bottomley@steeleye.com> | Thu Jul 26 17:13:10 2007 -0400 |
| committer | James Bottomley <jejb@mulgrave.localdomain> | Fri Jul 27 09:20:20 2007 -0400 |
| tree | abda8332877503a5a16f5138ab4298c6072a574b | |
| parent | 281afe1947d855661754850de29d7530b2ff18dc [diff] |
[SCSI] aic79xx, aic7xxx: Fix incorrect width setting Wide transfers are required for every setting of PPR apart from QAS. It seems the DV code starts at the minimum, which turns on DT and Wide regardless of the setting of max_width. Redo the PPR and period setting routines to respect max_width (i.e. start at period = 10 if it is zero). This fixes bugzilla 8366 Acked-by: "Freels, James D." <freelsjd@ornl.gov> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>