drm/i915/bxt: Program Tx Rx and Dphy clocks
BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
(Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro definition as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
v4: Addressed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87de3a0..8c24851 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7547,6 +7547,68 @@
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
+/* BXT MIPI clock controls */
+#define BXT_MAX_VAR_OUTPUT_KHZ 39500
+
+#define BXT_MIPI_CLOCK_CTL 0x46090
+#define BXT_MIPI1_DIV_SHIFT 26
+#define BXT_MIPI2_DIV_SHIFT 10
+#define BXT_MIPI_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
+ BXT_MIPI2_DIV_SHIFT)
+/* Var clock divider to generate TX source. Result must be < 39.5 M */
+#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
+#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
+#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
+ BXT_MIPI2_ESCLK_VAR_DIV_MASK)
+
+#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
+ (val << BXT_MIPI_DIV_SHIFT(port))
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define BXT_MIPI1_TX_ESCLK_SHIFT 21
+#define BXT_MIPI2_TX_ESCLK_SHIFT 5
+#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
+ BXT_MIPI2_TX_ESCLK_SHIFT)
+#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
+#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
+#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
+ BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
+ (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
+ (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
+ (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX control divider to select actual RX clock output from 8x*/
+#define BXT_MIPI1_RX_ESCLK_SHIFT 19
+#define BXT_MIPI2_RX_ESCLK_SHIFT 3
+#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
+ BXT_MIPI2_RX_ESCLK_SHIFT)
+#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
+#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
+#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
+ (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
+ (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+/* BXT-A WA: Always prog DPHY dividers to 00 */
+#define BXT_MIPI1_DPHY_DIV_SHIFT 16
+#define BXT_MIPI2_DPHY_DIV_SHIFT 0
+#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
+ BXT_MIPI2_DPHY_DIV_SHIFT)
+#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
+#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
+#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8