clk: meson-gxbb: Add EE 32K Clock for CEC
On Amlogic GX SoCs, there is two CEC controllers :
- An Amlogic CEC custom in the AO domain
- The Synopsys HDMI-TX Controller in the EE domain
Each of these controllers needs a 32.768KHz clock, but there is two paths :
- In the EE domain, the "32k_clk" this patchs is adding
- In the AO domain, with a more complex dual divider more precise setup
The AO 32K clock support will be pushed later in the corresponding
gxbb-aoclk driver when the AE CEC driver is ready.
The EE 32k_clk must be pushed earlier since mainline support for CEC in the
Synopsys HDMI-TX controller is nearby.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[Rebased patch on top of last changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 70f029a..d63e77e 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -284,8 +284,11 @@
#define CLKID_CTS_MCLK_I958_SEL 111
#define CLKID_CTS_MCLK_I958_DIV 112
/* CLKID_CTS_I958 */
+#define CLKID_32K_CLK 114
+#define CLKID_32K_CLK_SEL 115
+#define CLKID_32K_CLK_DIV 116
-#define NR_CLKS 114
+#define NR_CLKS 117
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>