| commit | 1526c704b3c32640b5e6cdc1662b0698603e9d4f | [log] [tgz] |
|---|---|---|
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | Mon Aug 14 06:22:14 2017 -0400 |
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | Sat Aug 26 13:51:57 2017 -0400 |
| tree | 27702798027d35c301dc4239d4eacb44559e8e29 | |
| parent | b24f021579c5384ea9ba22decec84e757d5fbd09 [diff] |
media: v4l: fwnode: The clock lane is the first lane in lane_polarities
The clock lane is the first lane in the lane_polarities array. Reflect this
consistently by putting the number of data lanes after the number of clock
lanes.
Fixes: 4ee236219f6d ("media: v4l2-fwnode: suppress a warning at OF parsing logic")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>