| commit | 98f3118debb3876399a8da59d72b4908431f1027 | [log] [tgz] |
|---|---|---|
| author | Joel Stanley <joel@jms.id.au> | Fri Dec 22 13:15:20 2017 +1030 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Fri Jan 26 16:22:43 2018 -0800 |
| tree | d8ea8be1990e7d1eb05b2602d640090acd786c5d | |
| parent | 99d01e0ec3415424210fcd345ebb0c516e4b7fa9 [diff] |
clk: aspeed: Add platform driver and register PLLs This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>