Merge remote-tracking branch 'lorenzo/pci/dwc' into next
* lorenzo/pci/dwc:
PCI: exynos: Fix a potential init_clk_resources NULL pointer dereference
PCI: iproc: Fix NULL pointer dereference for BCMA
PCI: dra7xx: Iterate over INTx status bits
PCI: dra7xx: Fix legacy INTD IRQ handling
PCI: qcom: Account for const type of of_device_id.data
PCI: dwc: artpec6: Fix return value check in artpec6_add_pcie_ep()
PCI: exynos: Remove deprecated PHY initialization code
PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
PCI: dwc: artpec6: Deassert the core before waiting for PHY
PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
PCI: dwc: artpec6: Add support for endpoint mode
bindings: PCI: artpec: Add support for endpoint mode
PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions
PCI: dwc: artpec6: Use BIT and GENMASK macros
PCI: dwc: artpec6: Remove unused defines
PCI: dwc: dra7xx: Help compiler to remove unused code
PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe
PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode
PCI: designware-ep: Add generic function for raising MSI irq
PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable
PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
PCI: dwc: Use the DMA-API to get the MSI address
pci: dwc: pci-dra7xx: Make shutdown handler static
Includes resolution to conflict between:
4494738de0d9 ("PCI: endpoint: Add the function number as argument to EPC ops")
6f6d7873711c ("PCI: designware-ep: Add generic function for raising MSI irq")
The resolution is due to Niklas Cassel <niklas.cassel@axis.com>:
https://lkml.kernel.org/r/20180201085608.GA22568@axis.com
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index e5d9d77..eae17d9 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -14,6 +14,7 @@
#ifndef _PCIE_DESIGNWARE_H
#define _PCIE_DESIGNWARE_H
+#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/msi.h>
#include <linux/pci.h>
@@ -100,10 +101,13 @@
#define MSI_MESSAGE_CONTROL 0x52
#define MSI_CAP_MMC_SHIFT 1
+#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
#define MSI_CAP_MME_SHIFT 4
#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
#define MSI_MESSAGE_ADDR_L32 0x54
#define MSI_MESSAGE_ADDR_U32 0x58
+#define MSI_MESSAGE_DATA_32 0x58
+#define MSI_MESSAGE_DATA_64 0x5C
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
@@ -168,7 +172,7 @@ struct pcie_port {
const struct dw_pcie_host_ops *ops;
int msi_irq;
struct irq_domain *irq_domain;
- unsigned long msi_data;
+ dma_addr_t msi_data;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
@@ -180,8 +184,8 @@ enum dw_pcie_as_type {
struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep);
- int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
- u8 interrupt_num);
+ int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type, u8 interrupt_num);
};
struct dw_pcie_ep {
@@ -196,10 +200,12 @@ struct dw_pcie_ep {
unsigned long ob_window_map;
u32 num_ib_windows;
u32 num_ob_windows;
+ void __iomem *msi_mem;
+ phys_addr_t msi_mem_phys;
};
struct dw_pcie_ops {
- u64 (*cpu_addr_fixup)(u64 cpu_addr);
+ u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size);
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
@@ -334,6 +340,9 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+ u8 interrupt_num);
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
#else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
{
@@ -347,5 +356,15 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
}
+
+static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+ u8 interrupt_num)
+{
+ return 0;
+}
+
+static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+}
#endif
#endif /* _PCIE_DESIGNWARE_H */