MIPS: features: Add initial support for TLBINVF capable cores
New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6130/
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index e71b491..e0a215f 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -351,6 +351,7 @@
#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
/*
* CPU ASE encodings