e1000e: cosmetic move of #defines and prototypes to the new ich8lan.h
Move #defines and function prototypes specific to the ICH/PCH family of
devices (ICH8/82562, ICH8/82566, ICH8/82567, ICH9/82562, ICH9/82566,
ICH9/82567, ICH10/82567, 82577, 82578, 82579, I217, I218) to the new
ich8lan.h header file (the convention for Intel wired ethernet drivers is
to use the name of the first device in the family for related file and
function names). These defines and function prototypes can be used by
other files in the driver and moving them to the ICH/PCH-family-specific
file makes it clearer to which devices they are applicable.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 8a145f4..21a9cc3 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -200,10 +200,6 @@
#define E1000_RA (E1000_RAL(0))
E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
- E1000_SHRAL_PCH_LPT_BASE = 0x05408,
-#define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
- E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
-#define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
@@ -215,6 +211,7 @@
E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
E1000_MANC = 0x05820, /* Management Control - RW */
E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
+ E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
E1000_HOST_IF = 0x08800, /* Host Interface */
E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
@@ -233,9 +230,6 @@
E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
E1000_FFLT_DBG = 0x05F04, /* Debug Register */
- E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
-#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
-#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
E1000_HICR = 0x08F00, /* Host Interface Control */
E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
@@ -272,10 +266,6 @@
#define BM_WUC_HOST_WU_BIT (1 << 4)
#define BM_WUC_ME_WU_BIT (1 << 5)
-#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
-#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
-#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
-
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
@@ -1004,5 +994,6 @@
#include "82571.h"
#include "80003es2lan.h"
+#include "ich8lan.h"
#endif