usb: phy: msm: Select secondary PHY via TCSR
Select the secondary PHY using the TCSR register, if phy-num=1
in the DTS (or phy_number is set in the platform data). The
SOC has 2 PHYs which can be used with the OTG port, and this
code allows configuring the correct one.
Note: This resolves the problem I was seeing where I couldn't
get the USB driver working at all on a dragonboard, from cold
boot. This patch depends on patch 5/14 from Ivan's msm USB
patch set. It does not use DT for the register address, as
there's no evidence that this address changes between SoC
versions.
Signed-off-by: Tim Bird <tim.bird@sonymobile.com>
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index db8d963..9437bcf 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -1489,6 +1489,7 @@
struct resource *res;
struct msm_otg *motg;
struct usb_phy *phy;
+ void __iomem *phy_select;
motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
if (!motg) {
@@ -1553,6 +1554,19 @@
if (IS_ERR(motg->regs))
return PTR_ERR(motg->regs);
+ /*
+ * NOTE: The PHYs can be multiplexed between the chipidea controller
+ * and the dwc3 controller, using a single bit. It is important that
+ * the dwc3 driver does not set this bit in an incompatible way.
+ */
+ if (motg->phy_number) {
+ phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
+ if (IS_ERR(phy_select))
+ return PTR_ERR(phy_select);
+ /* Enable second PHY with the OTG port */
+ writel_relaxed(0x1, phy_select);
+ }
+
dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
motg->irq = platform_get_irq(pdev, 0);