tree bb9add62acc4151b36c88b6bc893dc2000f08029
parent e723ff666a5da8f7fda4e36ebfeafac2175a5c6e
author Hans-Christian Egtvedt <hcegtvedt@atmel.com> 1198052959 +0100
committer Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 1208652008 -0400

avr32: Implement set_rate(), set_parent() and mode() for pll1

This patch is a take two of adding full functionality to PLL1 on
AT32AP7000.  This allows board-specific code and drivers to configure
and enable PLL1. This is useful when precise control over the
frequency of e.g. a genclock is needed and requested by users for the
ABDAC device.

The patch is based upon previous patches from both Haavard Skinnemoen
and David Brownell.

Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>