tree 33c33a65294d3e3ee6907fffc2e8fdab3fa070eb
parent 1166160ab531198f7abc773992c0e04d0f9b7600
author Romain Perier <romain.perier@gmail.com> 1440322357 +0200
committer Stephen Boyd <sboyd@codeaurora.org> 1441918530 -0700

clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>