tree afc655e39cee864255cb49657d4e30d1e0c549ac
parent 3967018ed67f9480b2f47f8908b44b66bdbd40b5
author Ben Widawsky <benjamin.widawsky@intel.com> 1380946974 -0700
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1381402029 +0200

drm/i915: Create GEN specific write MMIO

Similar to the previous patch which implemented GEN specific reads; this
patch does the same for writes. Writes have a bit of adding complexity
due to the FPGA_DBG feature of HSW plus:

gen[2-4]: nothing special
gen5: ILK dummy write
gen[6-7]: forcewake shenanigans
gen[HSW}: forcewake shenanigans + FPGA_DBG

I was a bit torn about whether or not to combine 6-HSW as one function,
since the FPGA_DBG is cleanly separated, and it wouldn't make the 6-7
MMIO too messy. In the end, I chose the clearest possible solution which
splits out HSW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>