ALSA: x86: Remove _v[12] suffices
Although we dropped the most of the obsoleted *_v1 definitions and
codes, some codes still keep the _v1 or _v2 suffices. Now they are
ripped off.
The only thing to be done carefully here is the definition of control
offsets. The original code defines enum hdmi_ctrl_reg_offset_v1 and
a few new elements just for v2 on its top. After this cleanup, we
remove the old AUD_HDMI_STATUS and AUD_HDMIW_INFOFR definitions and
replace with the v2 values.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 46db488..84b374c 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -249,10 +249,10 @@
channels = substream->runtime->channels;
else
channels = 2;
- cfg_val.cfg_regx_v2.num_ch = channels - 2;
+ cfg_val.cfg_regx.num_ch = channels - 2;
data = data | cfg_val.cfg_regval;
- mask = mask | AUD_CONFIG_CH_MASK_V2;
+ mask = mask | AUD_CONFIG_CH_MASK;
dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n",
__func__, data, mask);
@@ -265,10 +265,10 @@
u32 status_reg;
if (enable) {
- mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
+ mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
- mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS_v2, status_reg);
- mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
+ mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg);
+ mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
}
}
@@ -282,7 +282,7 @@
static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
u8 reset)
{
- had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, reset);
+ had_write_register(intelhaddata, AUD_HDMI_STATUS, reset);
}
/*
@@ -301,7 +301,7 @@
IEC958_AES0_NONAUDIO) >> 1;
ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
IEC958_AES3_CON_CLOCK) >> 4;
- cfg_val.cfg_regx_v2.val_bit = ch_stat0.status_0_regx.lpcm_id;
+ cfg_val.cfg_regx.val_bit = ch_stat0.status_0_regx.lpcm_id;
switch (substream->runtime->rate) {
case AUD_SAMPLE_RATE_32:
@@ -367,19 +367,19 @@
had_prog_status_reg(substream, intelhaddata);
- buf_cfg.buf_cfg_regx_v2.audio_fifo_watermark = FIFO_THRESHOLD;
- buf_cfg.buf_cfg_regx_v2.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
- buf_cfg.buf_cfg_regx_v2.aud_delay = 0;
+ buf_cfg.buf_cfg_regx.audio_fifo_watermark = FIFO_THRESHOLD;
+ buf_cfg.buf_cfg_regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
+ buf_cfg.buf_cfg_regx.aud_delay = 0;
had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
channels = substream->runtime->channels;
- cfg_val.cfg_regx_v2.num_ch = channels - 2;
+ cfg_val.cfg_regx.num_ch = channels - 2;
if (channels <= 2)
- cfg_val.cfg_regx_v2.layout = LAYOUT0;
+ cfg_val.cfg_regx.layout = LAYOUT0;
else
- cfg_val.cfg_regx_v2.layout = LAYOUT1;
+ cfg_val.cfg_regx.layout = LAYOUT1;
- cfg_val.cfg_regx_v2.val_bit = 1;
+ cfg_val.cfg_regx.val_bit = 1;
had_write_register(intelhaddata, AUD_CONFIG, cfg_val.cfg_regval);
return 0;
}
@@ -626,13 +626,13 @@
frame2.fr2_regx.chksum = -(checksum);
}
- had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, info_frame);
- had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame2.fr2_val);
- had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame3.fr3_val);
+ had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
+ had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.fr2_val);
+ had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.fr3_val);
/* program remaining DIP words with zero */
for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
- had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, 0x0);
+ had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
ctrl_state.ctrl_regx.dip_freq = 1;
ctrl_state.ctrl_regx.dip_en_sta = 1;
@@ -916,20 +916,20 @@
/* Handle Underrun interrupt within Audio Unit */
had_write_register(intelhaddata, AUD_CONFIG, 0);
/* Reset buffer pointers */
- had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 1);
- had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 0);
+ had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
+ had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
/*
* The interrupt status 'sticky' bits might not be cleared by
* setting '1' to that bit once...
*/
do { /* clear bit30, 31 AUD_HDMI_STATUS */
- had_read_register(intelhaddata, AUD_HDMI_STATUS_v2,
+ had_read_register(intelhaddata, AUD_HDMI_STATUS,
&hdmi_status);
dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
i++;
had_write_register(intelhaddata,
- AUD_HDMI_STATUS_v2, hdmi_status);
+ AUD_HDMI_STATUS, hdmi_status);
} else
break;
} while (i < MAX_CNT);
@@ -1812,7 +1812,7 @@
struct snd_intelhad *ctx = dev_id;
u32 audio_stat, audio_reg;
- audio_reg = AUD_HDMI_STATUS_v2;
+ audio_reg = AUD_HDMI_STATUS;
mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
if (audio_stat & HDMI_AUDIO_UNDERRUN) {