| commit | 48ed33c1b3737eb1324c1ae023a8eeccad60cef9 | [log] [tgz] |
|---|---|---|
| author | Paul Burton <paul.burton@imgtec.com> | Fri Aug 19 18:13:36 2016 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Tue Jan 03 16:48:40 2017 +0100 |
| tree | 2f0bba73f2155877df0790bbc863036f89bfb9e2 | |
| parent | d66f99bc46925831236cf2335fcc6087d34e2195 [diff] |
MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3 In systems with CM3 & higher, the L2 cache is inclusive of the L1 dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true and we avoid some unnecessary cache ops during DMA cache maintenance. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14018/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>