clk: meson: fractional pll support
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 73f0146..53326c3 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -40,7 +40,10 @@
u16 m;
u16 n;
u16 od;
+ u16 od2;
+ u16 frac;
};
+
#define PLL_RATE(_r, _m, _n, _od) \
{ \
.rate = (_r), \
@@ -49,12 +52,24 @@
.od = (_od), \
} \
+#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \
+ { \
+ .rate = (_r), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+ .od2 = (_od2), \
+ .frac = (_frac), \
+ } \
+
struct meson_clk_pll {
struct clk_hw hw;
void __iomem *base;
struct parm m;
struct parm n;
+ struct parm frac;
struct parm od;
+ struct parm od2;
const struct pll_rate_table *rate_table;
unsigned int rate_count;
spinlock_t *lock;