arm: davinci: Cleanup irq chip code
Make use of the new functionality which ensures that irq_set_type is
called with the chip masked. Unmask is only done when the interrupt is
not disabled.
Retrieve the trigger type from irq_data in unmask
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 20d66e5..f33d438 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -218,7 +218,7 @@
{
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
- unsigned status = irq_desc[d->irq].status;
+ unsigned status = irqd_get_trigger_type(d);
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
if (!status)
@@ -238,16 +238,6 @@
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
- irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
- irq_desc[d->irq].status |= trigger;
-
- /* don't enable the IRQ if it's currently disabled */
- if (irq_desc[d->irq].depth == 0) {
- __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
- ? &g->set_falling : &g->clr_falling);
- __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
- ? &g->set_rising : &g->clr_rising);
- }
return 0;
}
@@ -256,6 +246,7 @@
.irq_enable = gpio_irq_enable,
.irq_disable = gpio_irq_disable,
.irq_set_type = gpio_irq_type,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
};
static void
@@ -395,7 +386,7 @@
/* AINTC handles mask/unmask; GPIO handles triggering */
irq = bank_irq;
- gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
+ gpio_irqchip_unbanked = *irq_get_chip(irq);
gpio_irqchip_unbanked.name = "GPIO-AINTC";
gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
@@ -409,7 +400,7 @@
set_irq_chip(irq, &gpio_irqchip_unbanked);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_chip_data(irq, (__force void *) g);
- irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
+ irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
}
goto done;