| commit | 844ca23f5b2e9db925aa5fe0daa5d1d887dba84d | [log] [tgz] |
|---|---|---|
| author | Gabriel Fernandez <gabriel.fernandez@st.com> | Tue Dec 13 15:20:18 2016 +0100 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Wed Dec 21 16:09:12 2016 -0800 |
| tree | 959da94d6ee37ca14d0b51e7952e0cb58998b7e5 | |
| parent | 62710c121b262fb8fe26d50179ab407e421969ed [diff] |
clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or from pll-sai-p. The SDIO clock could be also derived from 48Mhz or from sys clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>