MIPS: MSI: Update MSI handling for XLP
The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.
PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index 6a40f24..3407495 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -178,13 +178,6 @@
else
nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
- /* Ack at eirr and PIC */
- ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
- if (cpu_is_xlp9xx())
- nlm_pic_ack(md->node->picbase,
- PIC_9XX_IRT_PCIE_LINK_INDEX(link));
- else
- nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
}
static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@
}
nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
- /* Ack at eirr and PIC */
- ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
if (!cpu_is_xlp9xx())
nlm_pic_ack(md->node->picbase,
PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@
do_IRQ(irqbase + i);
status &= status - 1;
}
+
+ /* Ack at eirr and PIC */
+ ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
+ if (cpu_is_xlp9xx())
+ nlm_pic_ack(md->node->picbase,
+ PIC_9XX_IRT_PCIE_LINK_INDEX(link));
+ else
+ nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
}
void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@
do_IRQ(irqbase + i);
status &= status - 1;
}
+ /* Ack at eirr and PIC */
+ ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
}