| commit | 553e9c1861b7f91492eb6e209adff81507624fa6 | [log] [tgz] |
|---|---|---|
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | Thu Jan 19 18:39:45 2017 +0200 |
| committer | Darren Hart <dvhart@linux.intel.com> | Sat Feb 04 02:47:23 2017 +0100 |
| tree | 18f4b811d8a098374d76a51acd06fdd28c47b025 | |
| parent | 4b819c6d5f3c9f9efb8ab334f735f6a223e84d14 [diff] |
platform/x86: intel_mid_powerbtn: Acknowledge interrupts Some platforms require interrupt to be acknowledged by clearing MSIC_PWRBTNM bit in interrupt level 1 mask register. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>