ARM: Add base support for ARMv7-M
This patch adds the base support for the ARMv7-M
architecture. It consists of the corresponding arch/arm/mm/ files and
various #ifdef's around the kernel. Exception handling is implemented by
a subsequent patch.
[ukleinek: squash in some changes originating from commit
b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)
from the v2.6.33-arm1 patch stack, port to post 3.6, drop zImage
support, drop reorganisation of pt_regs, assert CONFIG_CPU_V7M doesn't
leak into installed headers and a few cosmetic changes]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Jonathan Austin <jonathan.austin@arm.com>
Tested-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 0000000..fa88d09
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
+/*
+ * Common defines for v7m cpus
+ */
+#define V7M_SCS_ICTR IOMEM(0xe000e004)
+#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
+
+#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
+
+#define V7M_SCB_CPUID 0x00
+
+#define V7M_SCB_ICSR 0x04
+#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
+#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
+#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
+
+#define V7M_SCB_VTOR 0x08
+
+#define V7M_SCB_SCR 0x10
+#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
+
+#define V7M_SCB_CCR 0x14
+#define V7M_SCB_CCR_STKALIGN (1 << 9)
+
+#define V7M_SCB_SHPR2 0x1c
+#define V7M_SCB_SHPR3 0x20
+
+#define V7M_SCB_SHCSR 0x24
+#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
+#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
+#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
+
+#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
+#define V7M_xPSR_EXCEPTIONNO 0x000001ff
+
+/*
+ * When branching to an address that has bits [31:28] == 0xf an exception return
+ * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
+ * extension Bit [4] defines if the exception frame has space allocated for FP
+ * state information, SBOP otherwise. Bit [3] defines the mode that is returned
+ * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
+ * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
+ */
+#define EXC_RET_STACK_MASK 0x00000004
+#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd