clk: socfpga: update clk.h so for Arria10 platform to use
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..b09a5d5 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,9 +26,13 @@
#define CLKMGR_L4SRC 0x70
#define CLKMGR_PERPLL_SRC 0xAC
-#define SOCFPGA_MAX_PARENTS 3
+#define SOCFPGA_MAX_PARENTS 5
#define div_mask(width) ((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
extern void __iomem *clk_mgr_base_addr;
void __init socfpga_pll_init(struct device_node *node);