MIPS: Alchemy: platform: use clk framework for uarts
Use the clock framework to get the rate of the peripheral clock.
Remove the now obsolete get_uart_baud_base function.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7468/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 0e41416..a4c7cd7 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -38,7 +38,6 @@
#define AU1000_SRC_CLK 12000000
static unsigned int au1x00_clock; /* Hz */
-static unsigned long uart_baud_base;
/*
* Set the au1000_clock
@@ -55,21 +54,6 @@
EXPORT_SYMBOL(get_au1x00_speed);
/*
- * The UART baud base is not known at compile time ... if
- * we want to be able to use the same code on different
- * speed CPUs.
- */
-unsigned long get_au1x00_uart_baud_base(void)
-{
- return uart_baud_base;
-}
-
-void set_au1x00_uart_baud_base(unsigned long new_baud_base)
-{
- uart_baud_base = new_baud_base;
-}
-
-/*
* We read the real processor speed from the PLL. This is important
* because it is more accurate than computing it from the 32 KHz
* counter, if it exists. If we don't have an accurate processor
@@ -95,9 +79,6 @@
/* On Alchemy CPU:counter ratio is 1:1 */
mips_hpt_frequency = cpu_speed;
- /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
- set_au1x00_uart_baud_base(cpu_speed / (2 *
- ((alchemy_rdsys(AU1000_SYS_POWERCTRL) & 0x03) + 2) * 16));
set_au1x00_speed(cpu_speed);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index fb89d21..d77a64f 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
@@ -99,10 +100,20 @@
static void __init alchemy_setup_uarts(int ctype)
{
- unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
+ long uartclk;
int s = sizeof(struct plat_serial8250_port);
int c = alchemy_get_uarts(ctype);
struct plat_serial8250_port *ports;
+ struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
+
+ if (IS_ERR(clk))
+ return;
+ if (clk_prepare_enable(clk)) {
+ clk_put(clk);
+ return;
+ }
+ uartclk = clk_get_rate(clk);
+ clk_put(clk);
ports = kzalloc(s * (c + 1), GFP_KERNEL);
if (!ports) {