tree c0342e0d3614bab54473e59f144d849925a950fb
parent dce944dbb2d0046628bcdba882e8edc2c1d93200
author jassi brar <jassisinghbrar@gmail.com> 1251772508 +0900
committer Mark Brown <broonie@opensource.wolfsonmicro.com> 1251801461 +0100

ASoC: Debugged improper setting of PLL fields in WM8580 driver

Bug was caught while trying to use WM8580 as I2S master on SMDK.
Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved
by referring to WM8580A manual and setting mask value correctly and
making the code to not touch 'reserved' bits of PLL4 register.

Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>