tree 80e6471ee2c5dfebca74bbb7d4f90624cc03de00
parent 1001354ca34179f3db924eb66672442a173147dc
author Xing Zheng <zhengxing@rock-chips.com> 1477022620 +0800
committer Heiko Stuebner <heiko@sntech.de> 1477035259 +0200

clk: rockchip: add 533.25MHz to rk3399 clock rates table

We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>