commit 618dee3941a43d8d4f762a7af99bcb59baba2bc5
author Thierry Reding <treding@nvidia.com> Thu Jun 09 17:53:57 2016 +0200
committer Thierry Reding <treding@nvidia.com> Thu Jul 14 14:57:01 2016 +0200
tree f2d28fff57d07089847f8e5972a1e12af742cdd8
parent 5d2304c1de6b353a0e09f4ed22165835f5651e4b

drm/tegra: sor: Use sor1_src clock to set parent for HDMI

When running in HDMI mode, the sor1 IP block needs to use the sor1_src
as parent clock, and in turn configure the sor1_src to use pll_d2_out0
as its parent.

Signed-off-by: Thierry Reding <treding@nvidia.com>

drivers/gpu/drm/tegra/sor.c

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 896ba3b..26568ca 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -173,6 +173,7 @@
 	struct clk *clk_parent;
 	struct clk *clk_brick;
 	struct clk *clk_safe;
+	struct clk *clk_src;
 	struct clk *clk_dp;
 	struct clk *clk;
 
@@ -2101,7 +2102,11 @@
 	tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
 
 	/* switch to parent clock */
-	err = tegra_sor_set_parent_clock(sor, sor->clk_parent);
+	err = clk_set_parent(sor->clk_src, sor->clk_parent);
+	if (err < 0)
+		dev_err(sor->dev, "failed to set source clock: %d\n", err);
+
+	err = tegra_sor_set_parent_clock(sor, sor->clk_src);
 	if (err < 0)
 		dev_err(sor->dev, "failed to set parent clock: %d\n", err);
 
@@ -2595,6 +2600,16 @@
 		goto remove;
 	}
 
+	if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
+		sor->clk_src = devm_clk_get(&pdev->dev, "source");
+		if (IS_ERR(sor->clk_src)) {
+			err = PTR_ERR(sor->clk_src);
+			dev_err(sor->dev, "failed to get source clock: %d\n",
+				err);
+			goto remove;
+		}
+	}
+
 	sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
 	if (IS_ERR(sor->clk_parent)) {
 		err = PTR_ERR(sor->clk_parent);