ath9k: Initialize pll_pwrsave for AR9462/AR9565
Cards based on AR9462/AR9565 support more PCIE
power save mechanisms, so register them correctly.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index ca66fab..de862ad 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -440,6 +440,7 @@
/*
* The default value of pll_pwrsave is 1.
* For certain AR9485 cards, it is set to 0.
+ * For AR9462, AR9565 it's set to 7.
*/
ah->config.pll_pwrsave = 1;