Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0
ARM: S5P6442: Fix PLL setting announce message.
ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XX
ARM: S5PV210: Correct clock register properties
ARM: S5P: Bug fix on external interrupt for S5P SoCs
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index 3aadbf4..087e57f 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -294,7 +294,7 @@
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
- printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld",
+ printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
apll, mpll, epll);
clk_fout_apll.rate = apll;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..af91fef 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -183,6 +183,11 @@
return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
}
+static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
+}
+
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.id = -1,
@@ -406,14 +411,14 @@
.id = 0,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<4),
+ .ctrlbit = (1 << 5),
}, {
.name = "i2s_v32",
.id = 1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<4),
- }
+ .ctrlbit = (1 << 6),
+ },
};
static struct clk init_clocks[] = {
@@ -429,25 +434,25 @@
.id = 0,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<7),
+ .ctrlbit = (1 << 17),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<8),
+ .ctrlbit = (1 << 18),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<9),
+ .ctrlbit = (1 << 19),
}, {
.name = "uart",
.id = 3,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<10),
+ .ctrlbit = (1 << 20),
},
};
@@ -497,8 +502,8 @@
.clk = {
.name = "sclk_dac",
.id = -1,
- .ctrlbit = (1 << 10),
- .enable = s5pv210_clk_ip1_ctrl,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 2),
},
.sources = &clkset_sclk_dac,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +532,8 @@
.clk = {
.name = "sclk_hdmi",
.id = -1,
- .enable = s5pv210_clk_ip1_ctrl,
- .ctrlbit = (1 << 11),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 0),
},
.sources = &clkset_sclk_hdmi,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +570,8 @@
.clk = {
.name = "sclk_audio",
.id = 0,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 4),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 24),
},
.sources = &clkset_sclk_audio0,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +599,8 @@
.clk = {
.name = "sclk_audio",
.id = 1,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 5),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 25),
},
.sources = &clkset_sclk_audio1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +628,8 @@
.clk = {
.name = "sclk_audio",
.id = 2,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 6),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 26),
},
.sources = &clkset_sclk_audio2,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +685,8 @@
.clk = {
.name = "uclk1",
.id = 0,
- .ctrlbit = (1<<17),
- .enable = s5pv210_clk_ip3_ctrl,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 12),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +695,8 @@
.clk = {
.name = "uclk1",
.id = 1,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 18),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 13),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +705,8 @@
.clk = {
.name = "uclk1",
.id = 2,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 19),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 14),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +715,8 @@
.clk = {
.name = "uclk1",
.id = 3,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 20),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 15),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +725,8 @@
.clk = {
.name = "sclk_mixer",
.id = -1,
- .enable = s5pv210_clk_ip1_ctrl,
- .ctrlbit = (1 << 9),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 1),
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +743,8 @@
.clk = {
.name = "sclk_fimc",
.id = 0,
- .enable = s5pv210_clk_ip0_ctrl,
- .ctrlbit = (1 << 24),
+ .enable = s5pv210_clk_mask1_ctrl,
+ .ctrlbit = (1 << 2),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +753,8 @@
.clk = {
.name = "sclk_fimc",
.id = 1,
- .enable = s5pv210_clk_ip0_ctrl,
- .ctrlbit = (1 << 25),
+ .enable = s5pv210_clk_mask1_ctrl,
+ .ctrlbit = (1 << 3),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +763,8 @@
.clk = {
.name = "sclk_fimc",
.id = 2,
- .enable = s5pv210_clk_ip0_ctrl,
- .ctrlbit = (1 << 26),
+ .enable = s5pv210_clk_mask1_ctrl,
+ .ctrlbit = (1 << 4),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +773,8 @@
.clk = {
.name = "sclk_cam",
.id = 0,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 3),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +783,8 @@
.clk = {
.name = "sclk_cam",
.id = 1,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 4),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +793,8 @@
.clk = {
.name = "sclk_fimd",
.id = -1,
- .enable = s5pv210_clk_ip1_ctrl,
- .ctrlbit = (1 << 0),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 5),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +803,8 @@
.clk = {
.name = "sclk_mmc",
.id = 0,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1 << 16),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 8),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +813,8 @@
.clk = {
.name = "sclk_mmc",
.id = 1,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1 << 17),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 9),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +823,8 @@
.clk = {
.name = "sclk_mmc",
.id = 2,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1 << 18),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 10),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +833,8 @@
.clk = {
.name = "sclk_mmc",
.id = 3,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1 << 19),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 11),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +873,8 @@
.clk = {
.name = "sclk_csis",
.id = -1,
- .enable = s5pv210_clk_ip0_ctrl,
- .ctrlbit = (1 << 31),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 6),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +883,8 @@
.clk = {
.name = "sclk_spi",
.id = 0,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 12),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 16),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +893,8 @@
.clk = {
.name = "sclk_spi",
.id = 1,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 13),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 17),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +903,8 @@
.clk = {
.name = "sclk_pwi",
.id = -1,
- .enable = &s5pv210_clk_ip4_ctrl,
- .ctrlbit = (1 << 2),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 29),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +913,8 @@
.clk = {
.name = "sclk_pwm",
.id = -1,
- .enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1 << 23),
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 19),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index e56c807..f36cd33 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -71,7 +71,7 @@
break;
case IRQ_TYPE_EDGE_FALLING:
- newvalue = S5P_EXTINT_RISEEDGE;
+ newvalue = S5P_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..016674f 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -166,8 +166,10 @@
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
+static inline void s3c6410_default_sdhci2(void) { }
static inline void s3c6400_default_sdhci0(void) { }
static inline void s3c6400_default_sdhci1(void) { }
+static inline void s3c6400_default_sdhci2(void) { }
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
@@ -239,7 +241,7 @@
s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
}
#else
-static inline void s5pc100_default_sdhci0(void) { }
+static inline void s5pv210_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1