| commit | 6c00e7b76021fcf4ddb64191ccdf62c722adf0d1 | [log] [tgz] |
|---|---|---|
| author | Jerome Brunet <jbrunet@baylibre.com> | Fri Jan 19 16:42:36 2018 +0100 |
| committer | Jerome Brunet <jbrunet@baylibre.com> | Mon Feb 12 09:49:23 2018 +0100 |
| tree | 783c5d881ed9d73acbf63fb44eebc6bca9bd4b97 | |
| parent | 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 [diff] |
clk: meson: add axg misc bit to the mpll driver
On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
change (expect for mpll2 strangely). Looking at the vendor kernel, it
turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
is required.
Setting this bit solves the problem and the mpll rates are back to normal
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>