| commit | 6cf0716c0321344fdc72205d590e968e53492088 | [log] [tgz] |
|---|---|---|
| author | Jordan Justen <jordan.l.justen@intel.com> | Sun Mar 06 23:30:30 2016 -0800 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Mon Mar 21 10:03:26 2016 +0100 |
| tree | 75899e1fd24762d2a0a48c9d63a6bc2958e0b905 | |
| parent | 1b85066bb1332e4298e533b7f15e04d82990ceaf [diff] [blame] |
drm/i915: Bump command parser version for new whitelisted registers Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-6-git-send-email-jordan.l.justen@intel.com
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 546dfcc..a337f33 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1287,6 +1287,7 @@ * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. * 5. GPGPU dispatch compute indirect registers. + * 6. TIMESTAMP register and Haswell CS GPR registers */ - return 5; + return 6; }