| commit | 6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde | [log] [tgz] |
|---|---|---|
| author | Christoph Hellwig <hch@lst.de> | Sat Aug 04 10:23:16 2018 +0200 |
| committer | Palmer Dabbelt <palmer@sifive.com> | Mon Aug 13 08:31:31 2018 -0700 |
| tree | dc077f5075634c43587aa2658247e37b4004e59d | |
| parent | bec2e6ac353d5c8a47c6eea639136bac3990093e [diff] |
RISC-V: implement low-level interrupt handling Add support for a routine that dispatches exceptions with the interrupt flags set to either the IPI or irqdomain code (and the clock source in the future). Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>