MIPS: Add new option for unique RI/XI exceptions
MIPSr5 added support for unique exception codes for the Read-Inhibit
and Execute-Inhibit exceptions.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7338/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 3b9768e..eeb5400 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -32,6 +32,9 @@
#ifndef cpu_has_htw
#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
#endif
+#ifndef cpu_has_rixiex
+#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
+#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index ec6a0f9..7ba2a03 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -366,6 +366,7 @@
#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
+#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
/*
* CPU ASE encodings