tree 82a9e18779ffd332a6715f413cc8e5513ef7b667
parent 7662c8bd6545c12ac7b2b39e4554c3ba34789c50
author ling.ma@intel.com <ling.ma@intel.com> 1245898762 +0800
committer Eric Anholt <eric@anholt.net> 1246472444 -0700

drm/i915: Set SSC frequency for 8xx chips correctly

All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>