MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index db58bea..f991e77 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -76,14 +76,14 @@
#endif
#if CVMX_ENABLE_DEBUG_PRINTS
-#define cvmx_dprintf printk
+#define cvmx_dprintf printk
#else
#define cvmx_dprintf(...) {}
#endif
-#define CVMX_MAX_CORES (16)
-#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
-#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
+#define CVMX_MAX_CORES (16)
+#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
+#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
#define CAST64(v) ((long long)(long)(v))
#define CASTPTR(type, v) ((type *)(long)(v))
@@ -133,8 +133,8 @@
*
* Example: cvmx_build_bits(39,24,value)
* <pre>
- * 6 5 4 3 3 2 1
- * 3 5 7 9 1 3 5 7 0
+ * 6 5 4 3 3 2 1
+ * 3 5 7 9 1 3 5 7 0
* +-------+-------+-------+-------+-------+-------+-------+------+
* 000000000000000000000000___________value000000000000000000000000
* </pre>
@@ -183,7 +183,7 @@
* memory pointer (void *).
*
* @physical_address:
- * Hardware physical address to memory
+ * Hardware physical address to memory
* Returns Pointer to memory
*/
static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
@@ -207,10 +207,10 @@
/* We have a full 64bit ABI. Writing to a 64bit address can be done with
a simple volatile pointer */
-#define CVMX_BUILD_WRITE64(TYPE, ST) \
-static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
-{ \
- *CASTPTR(volatile TYPE##_t, addr) = val; \
+#define CVMX_BUILD_WRITE64(TYPE, ST) \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
+{ \
+ *CASTPTR(volatile TYPE##_t, addr) = val; \
}
@@ -221,19 +221,19 @@
/* We have a full 64bit ABI. Writing to a 64bit address can be done with
a simple volatile pointer */
-#define CVMX_BUILD_READ64(TYPE, LT) \
-static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
-{ \
+#define CVMX_BUILD_READ64(TYPE, LT) \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
+{ \
return *CASTPTR(volatile TYPE##_t, addr); \
}
/* The following defines 8 functions for writing to a 64bit address. Each
takes two arguments, the address and the value to write.
- cvmx_write64_int64 cvmx_write64_uint64
- cvmx_write64_int32 cvmx_write64_uint32
- cvmx_write64_int16 cvmx_write64_uint16
- cvmx_write64_int8 cvmx_write64_uint8 */
+ cvmx_write64_int64 cvmx_write64_uint64
+ cvmx_write64_int32 cvmx_write64_uint32
+ cvmx_write64_int16 cvmx_write64_uint16
+ cvmx_write64_int8 cvmx_write64_uint8 */
CVMX_BUILD_WRITE64(int64, "sd");
CVMX_BUILD_WRITE64(int32, "sw");
CVMX_BUILD_WRITE64(int16, "sh");
@@ -246,10 +246,10 @@
/* The following defines 8 functions for reading from a 64bit address. Each
takes the address as the only argument
- cvmx_read64_int64 cvmx_read64_uint64
- cvmx_read64_int32 cvmx_read64_uint32
- cvmx_read64_int16 cvmx_read64_uint16
- cvmx_read64_int8 cvmx_read64_uint8 */
+ cvmx_read64_int64 cvmx_read64_uint64
+ cvmx_read64_int32 cvmx_read64_uint32
+ cvmx_read64_int16 cvmx_read64_uint16
+ cvmx_read64_int8 cvmx_read64_uint8 */
CVMX_BUILD_READ64(int64, "ld");
CVMX_BUILD_READ64(int32, "lw");
CVMX_BUILD_READ64(int16, "lh");
@@ -389,7 +389,7 @@
/**
* Reads a chip global cycle counter. This counts CPU cycles since
- * chip reset. The counter is 64 bit.
+ * chip reset. The counter is 64 bit.
* This register does not exist on CN38XX pass 1 silicion
*
* Returns Global chip cycle count since chip reset.
@@ -453,7 +453,7 @@
/**
* Read a byte of fuse data
- * @byte_addr: address to read
+ * @byte_addr: address to read
*
* Returns fuse value: 0 or 1
*/