| commit | 7157c69a99510c2234fc0b6001f21776085fda73 | [log] [tgz] |
|---|---|---|
| author | Alex Frid <afrid@nvidia.com> | Tue Jul 25 13:34:15 2017 +0300 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Wed Aug 23 16:00:42 2017 -0700 |
| tree | 633a37c49cb0bb8320203a0f943fcec86bed93da | |
| parent | 71422dbb89ee4198c705ad14c75bfc72625f95c2 [diff] |
clk: tegra: Fix Tegra210 PLLU initialization - Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>