drm/i915: clear up backlight #define confusion on gen4+
- Regroup definitions for BLC_PWM_CTL so that they're all together and
and ordered according to the bitfields.
- Add all missing definitions for BLC_PWM_CTL2.
- Use the BLM_ (for backlight modulation) prefix consistently.
- Note that combination mode (i.e. also taking the legacy backlight
control value from pci config space into account) is gen4 only.
- Move the new registers for PCH-split machines up, they're an almost
match for the gen4 defitions. Prefix the special PCH-only bits with
BLM_PCH_. Also add the pipe C select bit for ivb.
- Rip out the second pair of PCH polarity definitions - they're only
valid on early (pre-production) ilk silicon.
- Adapt the existing code to use the new definitions. This has the
nice benefit of killing a magic (1 << 30) left behind be Jesse
Barnes.
No functional changes in this patch.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e76031..bad36e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6895,9 +6895,9 @@
* IVB has CPU eDP backlight regs too, set things up to let the
* PCH regs control the backlight
*/
- I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
+ I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
I915_WRITE(BLC_PWM_CPU_CTL, 0);
- I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
+ I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
}
void intel_modeset_init_hw(struct drm_device *dev)