drm/i915: pnv dpll doesn't use m1!
So don't try to store it in the DPLL_FP register.
Otherwise it looks like the limits for pineview are correct: It has
it's own clock computation code, which doesn't use an offset for n
divisors, and the register value based m limits look sane enough.
v2: Rebase on top of the pineview clock refactor and fixup up the
commit message: It's m1 pnv doens't care about, not m2!
Quoting Damien's review:
- "n can vary between 2 and 6, but we declare the 3-6 as limits.
- "p1 seems to be able to go up to 9
- "the m upper limit seems a bit big, but the docs are a bit shy on
that values for pnv.
"Otherwise, the change itself seems good:"
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bef9086..1dfaa1c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4240,7 +4240,7 @@
static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
{
- return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
+ return (1 << dpll->n) << 16 | dpll->m2;
}
static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)