Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next
- Various static analysis fixes/finds
- Video Engine (ECLK) support on Aspeed SoCs
- Xilinx ZynqMP Versal platform support
- Convert Xilinx ZynqMP driver to be struct oriented
* clk-sa:
clk: mvebu: fix spelling mistake "gatable" -> "gateable"
clk: ux500: add range to usleep_range
clk: tegra: Make tegra_clk_super_mux_ops static
clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5
* clk-aspeed:
clk: Aspeed: Setup video engine clocking
* clk-samsung:
clk: samsung: exynos5410: Add gate clock for ADC
clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
clk: samsung: dt-bindings: Put CLK_UART3 in order
* clk-ingenic:
clk: ingenic: jz4725b: Add UDC PHY clock
dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock
* clk-zynq:
clk: zynqmp: use structs for clk query responses
clk: zynqmp: fix check for fractional clock
clk: zynqmp: do not export zynqmp_clk_register_* functions
clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents
drivers: clk: Update clock driver to handle clock attribute
drivers: clk: zynqmp: Allow zero divisor value