commit 7f2ab69913135f0377a1dfc1da5695b64107d3ca
author Daniel Vetter <daniel.vetter@ffwll.ch> Mon Aug 02 17:06:59 2010 +0200
committer Chris Wilson <chris@chris-wilson.co.uk> Tue Sep 21 11:20:04 2010 +0100
tree a77229702de475d9184d78593aefc7bb2795ca5e
parent 570ef608591aa1c7f7cb615c2d33b30246179da1

drm/i915: use new macros to access the ring ctl register

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/intel_ringbuffer.c

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7eb936a..1198b60 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -145,7 +145,7 @@
 	obj_priv = to_intel_bo(ring->gem_object);
 
 	/* Stop the ring if it's running. */
-	I915_WRITE(ring->regs.ctl, 0);
+	I915_WRITE_CTL(ring, 0);
 	I915_WRITE_HEAD(ring, 0);
 	ring->set_tail(dev, ring, 0);
 
@@ -158,7 +158,7 @@
 		DRM_ERROR("%s head not reset to zero "
 				"ctl %08x head %08x tail %08x start %08x\n",
 				ring->name,
-				I915_READ(ring->regs.ctl),
+				I915_READ_CTL(ring),
 				I915_READ_HEAD(ring),
 				I915_READ_TAIL(ring),
 				I915_READ_START(ring));
@@ -168,13 +168,13 @@
 		DRM_ERROR("%s head forced to zero "
 				"ctl %08x head %08x tail %08x start %08x\n",
 				ring->name,
-				I915_READ(ring->regs.ctl),
+				I915_READ_CTL(ring),
 				I915_READ_HEAD(ring),
 				I915_READ_TAIL(ring),
 				I915_READ_START(ring));
 	}
 
-	I915_WRITE(ring->regs.ctl,
+	I915_WRITE_CTL(ring,
 			((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
 			| RING_NO_REPORT | RING_VALID);
 
@@ -184,7 +184,7 @@
 		DRM_ERROR("%s initialization failed "
 				"ctl %08x head %08x tail %08x start %08x\n",
 				ring->name,
-				I915_READ(ring->regs.ctl),
+				I915_READ_CTL(ring),
 				I915_READ_HEAD(ring),
 				I915_READ_TAIL(ring),
 				I915_READ_START(ring));
@@ -765,9 +765,6 @@
 static const struct intel_ring_buffer render_ring = {
 	.name			= "render ring",
 	.id			= RING_RENDER,
-	.regs                   = {
-		.ctl = PRB0_CTL,
-	},
 	.mmio_base		= RENDER_RING_BASE,
 	.size			= 32 * PAGE_SIZE,
 	.alignment		= PAGE_SIZE,
@@ -799,9 +796,6 @@
 static const struct intel_ring_buffer bsd_ring = {
 	.name                   = "bsd ring",
 	.id			= RING_BSD,
-	.regs			= {
-		.ctl = BSD_RING_CTL,
-	},
 	.mmio_base		= BSD_RING_BASE,
 	.size			= 32 * PAGE_SIZE,
 	.alignment		= PAGE_SIZE,
@@ -900,9 +894,6 @@
 static const struct intel_ring_buffer gen6_bsd_ring = {
        .name			= "gen6 bsd ring",
        .id			= RING_BSD,
-       .regs			= {
-               .ctl    = GEN6_BSD_RING_CTL,
-       },
        .mmio_base		= GEN6_BSD_RING_BASE,
        .size			= 32 * PAGE_SIZE,
        .alignment		= PAGE_SIZE,

drivers/gpu/drm/i915/intel_ringbuffer.h

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index af09eaa..1668cd9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -13,6 +13,8 @@
 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
+#define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base))
+#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
 
 struct drm_i915_gem_execbuffer2;
 struct  intel_ring_buffer {
@@ -21,9 +23,6 @@
 		RING_RENDER = 0x1,
 		RING_BSD = 0x2,
 	} id;
-	struct		ring_regs {
-			u32 ctl;
-	} regs;
 	u32		mmio_base;
 	unsigned long	size;
 	unsigned int	alignment;