commit 81c59f54125f9ff84546b6ba26c321662562703d
author Ken Wang <Qingqing.Wang@amd.com> Wed Jun 03 21:02:01 2015 +0800
committer Alex Deucher <alexander.deucher@amd.com> Wed Jun 03 21:04:04 2015 -0400
tree 5155dcf6e4f917f073d401342b412691e9757383
parent 71062f435eaf0ff7867a1188e5c7887b0a5871ff

drm/amdgpu: add vram_type and vram_bit_width for interface query (v2)

Track the type of vram on the board and provide a query for it.
User mode drivers and tools want this information for determining
bandwidth information and form informational purposes.

v2: fix build when CI support is not enabled

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>

drivers/gpu/drm/amd/amdgpu/cikd.h

diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index 11828e2..220865a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -24,9 +24,14 @@
 #ifndef CIK_H
 #define CIK_H
 
-#define MC_SEQ_MISC0__GDDR5__SHIFT	0x1c
-#define MC_SEQ_MISC0__GDDR5_MASK	0xf0000000
-#define MC_SEQ_MISC0__GDDR5_VALUE	5
+#define MC_SEQ_MISC0__MT__MASK	0xf0000000
+#define MC_SEQ_MISC0__MT__GDDR1  0x10000000
+#define MC_SEQ_MISC0__MT__DDR2   0x20000000
+#define MC_SEQ_MISC0__MT__GDDR3  0x30000000
+#define MC_SEQ_MISC0__MT__GDDR4  0x40000000
+#define MC_SEQ_MISC0__MT__GDDR5  0x50000000
+#define MC_SEQ_MISC0__MT__HBM    0x60000000
+#define MC_SEQ_MISC0__MT__DDR3   0xB0000000
 
 #define CP_ME_TABLE_SIZE    96