| commit | 853eb16b8b6a347315443f2ef010e5b97d8c1577 | [log] [tgz] |
|---|---|---|
| author | Lendacky, Thomas <Thomas.Lendacky@amd.com> | Tue Jul 29 08:57:31 2014 -0500 |
| committer | David S. Miller <davem@davemloft.net> | Wed Jul 30 18:46:52 2014 -0700 |
| tree | 2966ae65124b9dab3c1dc5c26ae887121505b2d3 | |
| parent | f047604a3ff1a1d7c8bd4a43c72de3936d71f3c1 [diff] |
amd-xgbe: Base queue fifo size and enablement on ring count When setting the fifo sizes for the queues and enabling the queues use the number of active Tx and Rx queues that have been enabled not the maximum number available. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>