tree 5f18745f77235b364f85c8b74804957b285cca4e
parent 8e8e523d865490e95ed7c9d2e173c02648d6be90
author Alex Deucher <alexdeucher@gmail.com> 1305880457 -0400
committer Dave Airlie <airlied@redhat.com> 1305885742 +1000

drm/radeon/kms: fix up DP clock programming on DCE4/5

In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic.  The crtc virtual pixel clock is derived from
the DP ref clock.

- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock

Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>