tree c0a636d952445b79d7e2301e1796b6c175c27c8a
parent 500a8cc466a24e2fbc4c86ef9c6467ae2ffdeb0c
author Zhenyu Wang <zhenyuw@linux.intel.com> 1263245911 +0800
committer Eric Anholt <eric@anholt.net> 1263593586 -0800

drm/i915: fix pixel color depth setting on eDP

Original DP mode_valid check didn't take pixel color depth into account,
which made one 1600x900 eDP panel's mode check invalid because of overclock,
but actually this 6bpc panel does can work with x1 lane at 2.7G. This one
trys to take bpp value properly both in mode validation and mode setting.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>